Arrow Lake Unveiled: Intel’s Strategy for Moving Beyond Raptors

In September 2023, Intel made headlines with the introduction of its new Meteor Lake System on Chip (SoC) tailored for the mobile market, marking a significant advancement as the first disaggregated chip in this sector, utilizing a tiled packaging approach. Despite general consensus suggesting that Meteor Lake failed to meet expectations, it nonetheless set the stage for Intel's continued exploration and innovation within the consumer technology landscape.

Following Meteor Lake, Intel is now focusing on its upcoming Lunar Lake processors, which aim to enhance efficiency and performance in the low-end to mid-range mobile segments. In tandem with these efforts, the company has also announced a new desktop platform aimed at reestablishing its footing in the market—Arrow Lake. This platform seeks to build on the successes of previous models while addressing the criticisms and issues associated with the instability of its earlier 14th Generation Raptor Lake Refresh chips.

A notable feature of the Arrow Lake desktop platform is the integration of Intel's AI-focused neural processing unit (NPU), which represents the first instance of such technology being included in Intel’s desktop products outside of its mobile-focused SoCs. Arrow Lake employs a disaggregated and scalable tiled manufacturing and design approach, with distinct tiles designated for computation, graphics, I/O, and the overall system-on-chip (SoC).

The context of Intel's announcement stems from a critical period in the company's history. In 2021, CEO Pat Gelsinger unveiled an ambitious roadmap promising five process nodes within four years. However, Intel has since faced a challenging trajectory, as evidenced by its recent lackluster financial performance.

Focusing on the technical specifications of the Arrow Lake processors, much attention was initially directed toward the anticipated 20A manufacturing node, which would mark a significant transition from traditional nanometer measurements to angstrom-based metrics. However, Intel’s decision to cancel the 20A node, which was to serve as a stepping stone to the subsequent 18A node, has led to adjustments in its production strategy. Despite the expectations that Intel would utilize its manufacturing capabilities for the Arrow Lake chips on the 20A node, the company has opted to outsource the tile manufacturing for this generation to TSMC. Intel will retain control over the packaging of the disaggregated architecture, utilizing its proprietary Foveros 3D stacking technology to assemble the tiles into a unified package, similar to its earlier Meteor Lake SoC architecture.

Starting with the compute tile, this element of Arrow Lake is being produced using TSMC's N3B node, which enables the introduction of two new core types into Intel's desktop lineup: Lion Cove (performance cores) and Skymont (efficiency cores).

The Lion Cove P-cores are specifically designed to optimize instructions per cycle (IPC) and single-threaded performance. Intel has claimed a performance improvement of up to 9% over the previous Raptor Lake P-cores. A significant architectural enhancement in these cores lies in the expanded out-of-order (OoO) execution engine. Intel has increased the allocation, renaming, and retirement stages of the pipeline, enabling the core to process more instructions per clock cycle. This improvement should enhance throughput during compute-heavy tasks, especially in parallel processing scenarios.

Another key aspect of Lion Cove is its enhanced branch prediction mechanism, which aims to reduce mispredictions—an expensive operation that can lead to pipeline stalls. By improving prediction accuracy and recovery latency, Lion Cove should achieve greater efficiency in dynamic workloads, particularly in areas like AI processing and gaming. Moreover, Intel has increased the size of the reorder buffer, allowing for more effective management of in-flight instructions, which bolsters out-of-order execution capabilities.

Intel has completely redesigned the cache hierarchy for the Lion Cove cores. The new structure includes a multi-level data cache with a 48KB L0D cache that boasts a low 4-cycle load-to-use latency, a 192KB L1D cache with a 9-cycle latency, and an expanded L2 cache, which is now 3MB per core. A larger cache is particularly beneficial in heavy-load scenarios, such as video editing and high-framerate gaming, as it minimizes the need for slower memory accesses.

The shared L3 cache has also been increased to 36MB, enhancing inter-core communication and overall multi-threaded performance—critical for workloads that involve multiple cores accessing shared data sets. Conversely, the Skymont E-cores present a significant upgrade over the previous Gracemont cores, with Intel claiming improvements of up to 32% in integer performance and as much as 72% in floating-point performance at identical clock speeds. Skymont cores are designed to be more power-efficient, handling background processes and parallel computation tasks while freeing the P-cores for more demanding workloads. Hyper-threading has been removed, allowing for one thread per core, which is intended to enhance power efficiency and thermal management.

A key architectural improvement in the Skymont cores is increased vector throughput through enhanced SIMD units, which permits more executions per data cycle. This enhancement is crucial for workloads in multimedia, AI, and scientific computing. The L2 cache per cluster has also increased from 2MB to 4MB, mitigating memory access bottlenecks and supporting better performance across multi-threaded applications.

The GPU tile within Arrow Lake is fabricated using TSMC's N5P process, an advanced version of the 5nm node. This GPU tile features four Xe-cores, each equipped with ray tracing units and enhanced vector engines, promising up to 2x the graphics performance compared to previous 14th Generation processors. It supports AI workloads through DP4a instructions and includes XeSS (Xe Super Sampling), which facilitates improved graphical output via AI-enhanced image upscaling.

While the GPU tile enhances performance and power efficiency, expectations should be tempered; integrated graphics may still struggle to handle AAA titles at maximum settings.

The SoC and I/O tile, designed on the TSMC N6 process node, oversees system connectivity and data flow within the Arrow Lake architecture. It supports high-bandwidth DDR5-6400 memory, enabling low-latency access to system resources, and manages up to 24 PCIe 5.0 lanes for swift data transfer to GPUs and NVMe SSDs. This tile also incorporates modern connectivity options, including Thunderbolt 4, Wi-Fi 7, and Bluetooth 5.4, ensuring Arrow Lake platforms are equipped with the latest communication standards. The N6 process strikes a balance between performance density and energy efficiency, allowing for high throughput with low power consumption.

Intel is introducing the new LGA 1851 socket alongside Arrow Lake, which will require a new range of motherboards to support the launch. The premium chipset accompanying Arrow Lake, named Z890, offers a variety of I/O options and configurations, featuring up to 24 PCIe 4.0 lanes, 10 USB 3.2 ports, 14 USB 2.0 ports, and 8 SATA ports. The specific implementation of these features will vary by motherboard vendors, with many premium models expected to offer USB4, Thunderbolt 4, and advanced consumer networking capabilities such as Wi-Fi 7 and even 10G Ethernet.

Intel's Arrow Lake platform represents a significant step forward in its desktop offerings, integrating advanced technologies and addressing past challenges while continuing to push the boundaries of efficiency and performance in both mobile and desktop markets. By leveraging cutting-edge manufacturing processes and innovative architectural designs, Intel aims to regain its competitive edge and offer compelling solutions to meet the evolving needs of consumers and businesses alike.